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LH28F800SG-L (FOR SOP)
LH28F800SG-L (FOR SOP)
DESCRIPTION
The LH28F800SG-L flash memory with Smart Voltage technology is a high-density, lowcost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F800SG-L can operate at VCC = 2.7 V and VPP = 2.7 V. Its low voltage operation capability realizes longer battery life and suits for cellular phone application. Its symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800SG-L offers three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking.These alternatives give designers ultimate control of their code security needs.
8 M-bit (512 kB x 16) SmartVoltage Flash Memory
* Enhanced data protection features - Absolute protection with VPP = GND - Flexible block locking - Block erase/word write lockout during power transitions * SRAM-compatible write interface * High-density symmetrically-blocked architecture - Sixteen 32 k-word erasable blocks * Enhanced cycling capability - 100 000 block erase cycles - 1.6 million block erase cycles/chip * Low power management - Deep power-down mode - Automatic power saving mode decreases ICC in static mode * Automated word write and block erase - Command user interface - Status register * ETOXTM V nonvolatile flash technology * Package - 44-pin SOP (SOP044-P-0600) ETOX is a trademark of Intel Corporation.
FEATURES
* SmartVoltage technology - 2.7 V, 3.3 V or 5 V VCC - 2.7 V, 3.3 V, 5 V or 12 V VPP * High performance read access time LH28F800SG-L70 - 70 ns (5.00.25 V)/80 ns (5.00.5 V)/ 85 ns (3.30.3 V)/100 ns (2.7 to 3.0 V) LH28F800SG-L10 - 100 ns (5.0 0.5 V)/100 ns (3.30.3 V)/ 120 ns (2.7 to 3.0 V) * Enhanced automated suspend options - Word write suspend to read - Block erase suspend to word write - Block erase suspend to read
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH28F800SG-L (FOR SOP)
COMPARISON TABLE
VERSIONS LH28F800SG-L (FOR SOP) LH28F800SG-L1 (FOR TSOP, CSP) LH28F800SGH-L1 (FOR TSOP, CSP) OPERATING TEMPERATURE 0 to +70C 0 to +70C - 40 to +85C PACKAGE 44-pin SOP 48-pin TSOP (I) 48-ball CSP 48-pin TSOP (I) 48-ball CSP WRITE PROTECT FUNCTION Controlled by RP# pin Controlled by WP# and RP# pins Controlled by WP# and RP# pins
1 Refer to the datasheet of LH28F800SG-L/SGH-L (FOR TSOP, CSP).
PIN CONNECTIONS
44-PIN SOP
VPP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
TOP VIEW
RP# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 NC GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
(SOP044-P-0600)
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LH28F800SG-L (FOR SOP)
BLOCK DIAGRAMS
DQ0-DQ15
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
IDENTIFIER REGISTER DATA REGISTER
I/O LOGIC
VCC CE#
STATUS REGISTER
COMMAND USER INTERFACE
WE# OE# RP#
DATA COMPARATOR
A0-A18
INPUT BUFFER
Y DECODER
Y GATING
WRITE STATE MACHINE
RY/BY#
PROGRAM/ERASE VOLTAGE SWITCH
VPP
ADDRESS LATCH
X DECODER
16 32 k-WORD BLOCKS
VCC GND
ADDRESS COUNTER
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LH28F800SG-L (FOR SOP)
PIN DESCRIPTION
SYMBOL A0-A18 TYPE INPUT NAME AND FUNCTION ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs DQ0-DQ15 INPUT/ OUTPUT data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense CE# INPUT amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provide data protection during power transitions. Exit from deep RP# INPUT power-down sets the device to read array mode. RP# at VHH allows to set permanent lock-bit. Block erase, word write, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted. OE# WE# INPUT INPUT OUTPUT ENABLE : Controls the device's outputs during a read cycle. WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, word write, or lock-bit configuration). RY/BY# OUTPUT RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and word write is inactive, word write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing word, or configuring lock-bits. With VPP VPPLK, VPP SUPPLY memory contents cannot be altered. Block erase, word write, and lock-bit configuration with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or 5 V operation. To switch from one voltage to another, ramp VCC down to GND and then VCC SUPPLY ramp VCC to the new voltage. Do not float any power pins. With VCC VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. GROUND : Do not float any ground pins. NO CONNECT : Lead is not internal connected; recommend to be floated.
GND NC
SUPPLY
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LH28F800SG-L (FOR SOP)
1 INTRODUCTION
This datasheet contains LH28F800SG-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F800SG-L flash memory documentation also includes ordering information which is referenced in Section 7. the power of 5 V VCC. But, 5 V VCC provides the highest read performance. VPP at 2.7 V, 3.3 V and 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and word write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP VPPLK.
Table 1 VCC and VPP Voltage Combinations Offered by SmartVoltage Technology VCC VOLTAGE 2.7 V 3.3 V 5V VPP VOLTAGE 2.7 V, 3.3 V, 5 V, 12 V 3.3 V, 5 V, 12 V 5 V, 12 V
1.1
New Features
Key enhancements of LH28F800SG-L SmartVoltage flash memory are : * * * * SmartVoltage Technology Enhanced Suspend Capabilities In-System Block Locking Permanent Lock Capability
Note following important differences : * VPPLK has been lowered to 1.5 V to support 3.3 V and 5 V block erase, word write, and lockbit configuration operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND. * To take advantage of SmartVoltage technology, allow VCC connection to 2.7 V, 3.3 V or 5 V. * Once set the permanent lock bit, the blocks which have been set block lock-bit can not be erased, written forever.
Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations. A command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timing necessary for block erase, word write, and lock-bit configuration operations. A block erase operation erases one of the device's 32 k-word blocks typically within 1.2 second (5 V VCC, 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. Writing memory data is performed in word increments typically within 7.5 s (5 V VCC, 12 V VPP). Word write suspend mode enables the system to read data from, or write data to any other flash memory array location.
1.2
Product Overview
The LH28F800SG-L is a high-performance 8 M-bit SmartVoltage flash memory organized as 512 kword of 16 bits. The 512 k-word of data is arranged in sixteen 32 k-word blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Fig. 1. SmartVoltage technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7 to 3.6 V VCC consumes approximately one-fifth
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LH28F800SG-L (FOR SOP)
The selected block can be locked or unlocked individually by the combination of sixteen block lock bits and the RP#. Block erase or word write must not be carried out by setting block lock bits and RP# to VIH. Even if RP# is set to VHH, block erase and word write to locked blocks is prohibited by setting permanent lock bit. The status register or RY/BY# indicates when the WSM's block erase, word write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, word write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep power-down mode. The access time is 70 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range (0 to +70C). At 4.5 to 5.5 V VCC, the access time is 80 ns or 100 ns. At lower VCC voltage, the access time is 85 ns or 100 ns (3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V). The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC and 3 mA at 2.7 to 3.6 V VCC. When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.
7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000
32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block 32 k-Word Block
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig. 1 Memory Map
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LH28F800SG-L (FOR SOP)
2 PRINCIPLES OF OPERATION
The LH28F800SG-L SmartVoltage flash memory includes an on-chip WSM to manage block erase, word write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, word write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, word writing, and lock-bit configuration. All functions associated with altering memory contents -- block erase, word write, lockbit configuration, status, and identifier codes -- are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, word write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, word write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, word writes, or lock-bit configurations are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, word write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating erase and word write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
3.1
Read
Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read
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LH28F800SG-L (FOR SOP)
array mode. Four control pins dictate the data flow in and out of the component : CE#, OE#, WE# and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 13 illustrates read cycle. During block erase, word write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, word write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.
3.3
Standby
CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, word write, or lockbit configuration, the device continues functioning, and consuming active power until the operation completes.
3.4
Deep Power-Down
RP# at VIL initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.
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LH28F800SG-L (FOR SOP)
3.5
Read Identifier Codes
3.6
Write
The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the permanent lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting.
Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word Write command requires the command and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 14 and Fig. 15 illustrate WE# and CE# controlled write operations.
7FFFF
78004 78003 78002 78001 78000
Reserved for Future Implementation
Block 15 Lock Configuration Code Reserved for Future Implementation Block 15 (Blocks 2 through 14)
0FFFF
08004 08003 08002 08001 08000 07FFF
Reserved for Future Implementation
4 COMMAND DEFINITIONS
Block 1 Lock Configuration Code Reserved for Future Implementation
Block 1
When the VPP VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2/3 on VPP enables successful block erase, word write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.
Reserved for Future Implementation
00004 00003 00002 00001 00000
Permanent Lock Configuration Code Block 0 Lock Configuration Code Device Code Manufacture Code Block 0
Fig. 2 Device Identifier Code Memory Map
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LH28F800SG-L (FOR SOP)
Table 2 Bus Operations MODE Read Output Disable Standby Deep Power-Down Read Identifier Codes Write NOTE 3 3 4 RP# VIH or VHH VIH or VHH VIL CE# VIL VIL VIH X VIL VIL OE# VIL VIH X X VIL VIH
4. 5. 6. 7. 8.
WE# VIH VIH X X VIH VIL
ADDRESS X X X X See Fig. 2 X
VPP X X X X X X
DQ0-15 DOUT High Z High Z High Z (NOTE 5) DIN
RY/BY# X X X VOH VOH X
1, 2, 3, 8 VIH or VHH
8 VIH or VHH 3, 6, 7, 8 VIH or VHH
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP VPPLK, memory contents can be read, but not altered. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages. RY/BY# is VOL when the WSM is executing internal block erase, word write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with word write inactive), word write suspend mode, or deep power-down mode. RP# at GND0.2 V ensures the lowest deep powerdown current. See Section 4.2 for read identifier code data. VIH < RP# < VHH produce spurious results and should not be attempted. Refer to Table 3 for valid DIN during a write operation. Don't use the timing both OE# and WE# are VIL.
2.
3.
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LH28F800SG-L (FOR SOP)
Table 3 Command Definitions (NOTE 9) COMMAND Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume Set Block Lock-Bit Set Permanent Lock-Bit Clear Block Lock-Bits BUS CYCLES REQ'D. 1 2 2 1 2 2 1 1 2 2 2 5 5, 6 5 5 7 7 8 NOTE FIRST BUS CYCLE SECOND BUS CYCLE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Write X FFH Write Write Write Write Write Write Write Write Write Write
6. 7.
4
X X X BA WA X X BA X X
90H 70H 50H 20H 40H or 10H B0H D0H 60H 60H 60H
Read Read Write Write
IA X BA WA
ID SRD D0H WD
Write Write Write
BA X X
01H F1H D0H
NOTES :
1. 2. Bus operations are defined in Table 2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. BA = Address within the block being erased or locked. WA = Address of memory location to be written. SRD = Data read from status register. See Table 6 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and permanent lock codes. See Section 4.2 for read identifier code data. If the block is locked and the permanent lock-bit is not set, RP# must be at VHH to enable block erase or word write operations. Attempts to issue a block erase or word write to a locked block while RP# is VHH. Either 40H or 10H is recognized by the WSM as the word write setup. If the permanent lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the permanent lock-bit. If the permanent lock-bit is set, a block lock-bit cannot be set. Once the permanent lock-bit is set, permanent lock-bit reset is unable. If the permanent lock-bit is set, clear block lock-bits operation is unable. The clear block lock-bits operation simultaneously clears all block lock-bits. If the permanent lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VHH. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
3.
8.
4.
9.
5.
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LH28F800SG-L (FOR SOP)
4.1
Read Array Command
4.3
Read Status Register Command
Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, word write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH.
The status register may be read to determine when a block erase, word write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH.
4.2
Read Identifier Codes Command 4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or word write suspend modes.
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and permanent lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read :
Table 4 Identifier Codes CODE ADDRESS DATA Manufacture Code 00000H 00B0H Device Code 00001H 0050H Block Lock Configuration (NOTE 2) XX002H (NOTE 1) * Unlocked DQ0 = 0 * Locked DQ0 = 1 * Reserved for future enhancement DQ1-15 Permanent Lock Configuration (NOTE 2) 00003H * Unlocked DQ0 = 0 * Locked DQ0 = 1 * Reserved for future enhancement DQ1-15
4.5
Block Erase Command
NOTES :
1. 2. X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map. Block lock status and permanent lock status are output by DQ0. DQ1-DQ15 are reserved for future enhancement.
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written,
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LH28F800SG-L (FOR SOP)
the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to "1". Once permanent lock-bit is set, the blocks which have been set block lock-bit are unable to erase forever. Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted. completion of the word write event by analyzing the RY/BY# pin or status register bit SR.7. When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word writes can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against word writes. If word write is attempted while VPP VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If word write is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1". Once permanent lock-bit is set, the blocks which have been set block lock-bit are unable to write forever. Word write operations with VIH < RP# < VHH produce spurious results and should not be attempted.
4.7
Block Erase Suspend Command
4.6
Word Write Command
Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the
The Block Erase Suspend command allows block erase interruption to read or word write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency.
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LH28F800SG-L (FOR SOP)
At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word Write Suspend command (see Section 4.8), a word write operation can also be suspended. During a word write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 5). VPP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until word write operations initiated during block erase suspend have completed. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the word write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Fig. 6). VPP must remain at VPPH1/2/3 (the same VPP level used for word write) while in word write suspend mode. RP# must also remain at VIH or VHH (the same RP# level used for word write).
4.9
Set Block and Permanent LockBit Commands
4.8
Word Write Suspend Command
The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM suspend the word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH1 defines the word write suspend latency.
The combination of the software command sequence and hardware RP# pin provides most flexible block lock (write protection) capability. The word write/block erase operation is restricted by the status of block lock-bit, RP# pin and permanent lock-bit. The status of RP# pin and permanent lockbit restricts the set block bit. When the permanent lock-bit has not been set, and when RP# = VHH, the block lock bit can be set with the status of the RP# pin. When RP# = VHH, the permanent lock-bit can be set with the permanent lock-bit set command. After the permanent lock-bit has been set, the write/erase operation to the block lock-bit can never be accepted. Refer to Table 5 for the hardware and the software write protection. Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device
- 14 -
LH28F800SG-L (FOR SOP)
automatically outputs status register data when read (see Fig. 7). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, lockbit contents are protected against alteration. A successful set block lock-bit operation requires that the permanent lock-bit be cleared and RP# = VHH. If it is attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set permanent lock-bit operation requires that RP# = VHH. If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set permanent lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted. Clear block lock-bits option is executed by a twocycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Fig. 8). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block LockBits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In a clear block lock-bits operation is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are protected against alteration. A successful clear block lock-bits operation requires that the permanent lock-bit is not set and RP# = VHH. If it is attempted with the permanent lock-bit set or RP# = VIH, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transition out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set, it cannot be cleared.
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the permanent lock-bit not set and RP# = VHH, block lock-bits can be cleared using the Clear Block LockBits command. If the permanent lock-bit is set, clear block lock-bits operation is unable. See Table 5 for a summary of hardware and software write protection options.
- 15 -
LH28F800SG-L (FOR SOP)
Table 5 Write Protection Alternatives PERMANENT BLOCK OPERATION RP# LOCK-BIT LOCK-BIT VIH or VHH X 0 Block Erase VHH or 0 1 VIH Word Write 1 X VHH Set Block 0 VIH X Lock-Bit 1 X Set Permanent VHH X X Lock-Bit VIH VHH Clear Block 0 VIH X Lock-Bits 1 X EFFECT Block Erase and Word Write Enabled Block Lock-Bit Override. Block Erase and Word Write Enabled Block is Locked. Block Erase and Word Write Disabled Permanent Lock-Bit is set. Block Erase and Word Write Disabled Set Block Lock-Bit Enabled Set Block Lock-Bit Disabled Permanent Lock-Bit is set. Set Block Lock-Bit Disabled Set Permanent Lock-Bit Enabled Set Permanent Lock-Bit Disabled Clear Block Lock-Bits Enabled Clear Block Lock-Bits Disabled Permanent Lock-Bit is set. Clear Block Lock-Bits Disabled
Table 6 Status Register Definition
WSMS 7
ESS 6
ECLBS 5
WWSLBS 4
VPPS 3 NOTES :
WWSS 2
DPS 1
R 0
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed
Check RY/BY# or SR.7 to determine block erase, word write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) SR.3 does not provide a continuous indication of VPP level. 1 = Error in Block Erase or Clear Lock-Bits The WSM interrogates and indicates the VPP level only after 0 = Successful Block Erase or Clear Lock-Bits SR.4 = WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS) 1 = Error in Word Write or Set Permanent/Block Lock-Bit 0 = Successful Word Write or Set Permanent/Block Lock-Bit SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = WORD WRITE SUSPEND STATUS (WWSS) 1 = Word Write Suspended 0 = Word Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Permanent Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Block Erase, Word Write, Set Block/Permanent Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPP VPPH1/2/3. SR.1 does not provide a continuous indication of permanent and block lock-bit values. The WSM interrogates the permanent lock-bit, block lock-bit, and RP# only after Block Erase, Word Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set, and/or RP# is not VHH. Reading the block lock and permanent lock configuration codes after writing the Read Identifier Codes command indicates permanent and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register.
- 16 -
LH28F800SG-L (FOR SOP)
Start
BUS OPERATION COMMAND Write Write Erase Setup Erase Confirm
COMMENTS Data = 20H Addr = Within Block to be Erased Data = D0H Addr = Within Block to be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 20H, Block Address
Write D0H, Block Address
Read
Standby
Read Status Register No 0 SR.7 = 1 Full Status Check if Desired Suspend Block Erase Loop Yes
Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last block erase operation to place device in read array mode.
Suspend Block Erase
Block Erase Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS OPERATION COMMAND Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
SR.3 = 0
1
VPP Range Error
Standby
SR.1 = 0
1
Device Protect Error
Standby Standby
SR.4, 5 = 0
1
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
SR.5 = 0 Block Erase Successful
1
Block Erase Error
Fig. 3 Automated Block Erase Flowchart
- 17 -
LH28F800SG-L (FOR SOP)
Start
BUS OPERATION COMMAND Write Write Setup Word Write Word Write
COMMENTS Data = 40H Addr = Location to be Written Data = Data to be Written Addr = Location to be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H, Address
Write Word Data and Address
Read
Standby
Read Status Register No 0 SR.7 = 1 Full Status Check if Desired Suspend Word Write Loop
Repeat for subsequent word writes. SR full status check can be done after each word write or after a sequence of word writes. Write FFH after the last word write operation to place device in read array mode.
Suspend Yes Word Write
Word Write Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS OPERATION COMMAND Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4 1 = Data Write Error
SR.3 = 0
1
VPP Range Error
Standby
SR.1 = 0
1
Device Protect Error
Standby
SR.4 = 0 Word Write Successful
1
Word Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery.
Fig. 4 Automated Word Write Flowchart
- 18 -
LH28F800SG-L (FOR SOP)
Start
BUS OPERATION Write
COMMAND Erase Suspend
COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed
Write B0H
Read
Read Status Register
Standby
SR.7 = 1 SR.6 = 1 Read Read or Word Write?
0
Standby Erase Resume
Write
Data = D0H Addr = X
0
Block Erase Completed
Word Write
Read Array Data
Word Write Loop No
Done? Yes Write D0H Write FFH
Block Erase Resumed
Read Array Data
Fig. 5 Block Erase Suspend/Resume Flowchart
- 19 -
LH28F800SG-L (FOR SOP)
Start
BUS OPERATION Write
COMMAND Word Write Suspend
COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Word Write Suspended 0 = Word Write Completed
Write B0H
Read
Read Status Register
Standby
0 SR.7 = 1 SR.2 = 1 Write FFH 0 Word Write Completed
Standby
Write Read
Read Array
Data = FFH Addr = X Read array locations other than that being written.
Write
Word Write Resume
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Word Write Resumed
Read Array Data
Fig. 6 Word Write Suspend/Resume Flowchart
- 20 -
LH28F800SG-L (FOR SOP)
Start
BUS OPERATION
COMMAND Set Block/Permanent Lock-Bit Setup
COMMENTS Data = 60H Addr = Block Address (Block), Device Address (Permanent)
Write 60H, Block/Device Address
Write
Write 01H/F1H, Block/Device Address
Write
Set Data = 01H (Block), Block or Permanent F1H (Permanent) Lock-Bit Addr = Block Address (Block), Confirm Device Address (Permanent) Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Read Status Register
Read
Standby
0 SR.7 = 1 Full Status Check if Desired
Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS OPERATION COMMAND Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH (Set Permanent Lock-Bit Operation) RP# = VIH or Permanent Lock-Bit is Set (Set Block Lock-Bit Operation) Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error
SR.3 = 0
1
VPP Range Error
Standby
SR.1 = 0
1
Device Protect Error
Standby
SR.4, 5 = 0
1
Command Sequence Error
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked.
SR.4 = 0 Set Lock-Bit Successful
1
Set Lock-Bit Error
If error is detected, clear the status register before attempting retry or other error recovery.
Fig. 7 Set Block and Permanent Lock-Bit Flowchart
- 21 -
LH28F800SG-L (FOR SOP)
Start
BUS OPERATION Write
COMMAND Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
COMMENTS Data = 60H Addr = X Data = D0H Addr = X
Write 60H
Write
Write D0H
Read
Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Read Status Register
Standby
SR.7 = 1
0
Write FFH after the last clear block lock-bits operation to place device in read array mode.
Full Status Check if Desired
Clear Block Lock-Bits Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
BUS OPERATION COMMAND Standby
COMMENTS Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH or Permanent Lock-Bit is Set Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error
1 SR.3 = 0 1 Device Protect Error VPP Range Error
Standby
SR.1 = 0
Standby Standby
1 SR.4, 5 = 0 1
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the status register before attempting retry or other error recovery.
SR.5 = 0
Clear Block Lock-Bits Error
Clear Block Lock-Bits Successful
Fig. 8 Clear Block Lock-Bits Flowchart
- 22 -
LH28F800SG-L (FOR SOP)
5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control
The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Threeline control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.4
VPP Trace on Printed Circuit Boards
5.2
RY/BY# and Block Erase, Word Write, and Lock-Bit Configuration Polling
RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, word write and lock-bit configuration completion. It transitions low after block erase, word write, or lockbit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also VOH when the device is in block erase suspend (with word write inactive), word write suspend or deep power-down modes.
Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for word writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
5.5
VCC, VPP, RP# Transitions
5.3
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current
Block erase, word write and lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2/3 range, VCC falls outside of a valid VCC1/2/3/4 range, or RP# VIH or VHH. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, word write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be
- 23 -
LH28F800SG-L (FOR SOP)
repeated after normal operation is restored. Device power-off or RP# transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO. After block erase, word write, or lock-bit configuration, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired.
5.7
Power Consumption
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solidstate storage can consume negligible power by lowering RP# to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP# is first raised to VIH. See Section 6.2.4 through 6.2.6 "AC CHARACTERISTICS - READ-ONLY and WRITE OPERATIONS" and Fig. 13, Fig. 14 and Fig. 15 for more information.
5.6
Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, word writing, or lock-bit configuration during power transitions. Upon powerup, the device is indifferent as to which power supply (VPP or VCC) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = VIL regardless of its control inputs state.
- 24 -
LH28F800SG-L (FOR SOP)
6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings
Operating Temperature During Read, Block Erase, Word Write and Lock-Bit Configuration ...... 0 to +70C (NOTE 1) Temperature under Bias ............. -10 to +80C Storage Temperature ....................... - 65 to +125C Voltage On Any Pin (except VCC, VPP, and RP#) .... -2.0 to +7.0 V (NOTE 2) VCC Supply Voltage ................. -2.0 to +7.0 V (NOTE 2)
NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. WARNING : Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES :
1. 2. Operating temperature is for commercial product defined by this specification. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and - 0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5 V which, during transitions, may overshoot to VCC+2.0 V for periods < 20 ns. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods < 20 ns. Output shorted for no more than one second. No more than one output shorted at a time.
VPP Update Voltage during Block Erase, Word Write and Lock-Bit Configuration .. -2.0 to +14.0 V (NOTE 2, 3) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations .. -2.0 to +14.0 V (NOTE 2, 3) Output Short Circuit Current .............. 100 mA (NOTE 4)
3. 4.
6.2
Operating Conditions
NOTE 1 MIN. 0 2.7 3.0 4.75 4.50 MAX. +70 3.0 3.6 5.25 5.50 UNIT C V V V V LH28F800SG-L70 VERSION
SYMBOL PARAMETER TA Operating Temperature VCC1 VCC2 VCC3 VCC4 VCC Supply Voltage (2.7 to 3.0 V) VCC Supply Voltage (3.30.3 V) VCC Supply Voltage (5.00.25 V) VCC Supply Voltage (5.00.5 V)
NOTE :
1. Test condition : Ambient temperature
6.2.1 CAPACITANCE (NOTE 1)
TA = +25C, f = 1 MHz SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance TYP. 7 9 MAX. 10 12 UNIT pF pF CONDITION VIN = 0.0 V VOUT = 0.0 V
NOTE :
1. Sampled, not 100% tested.
- 25 -
LH28F800SG-L (FOR SOP) 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7 INPUT 0.0 1.35 TEST POINTS 1.35 OUTPUT
AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 9 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.0 V
3.0 INPUT 0.0 1.5 TEST POINTS 1.5 OUTPUT
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 10 Transient Input/Output Reference Waveform for VCC = 3.30.3 V and VCC = 5.00.25 V (High Speed Testing Configuration)
2.4 INPUT 0.45
2.0 TEST POINTS 0.8
2.0 OUTPUT 0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 11 Transient Input/Output Reference Waveform for VCC = 5.00.5 V (Standard Testing Configuration) Test Configuration Capacitance Loading Value
1.3 V 1N914
TEST CONFIGURATION VCC = 3.30.3 V, 2.7 to 3.0 V VCC = 5.00.25 V (NOTE 1) VCC = 5.00.5 V
CL (pF) 50 30 100
NOTE :
RL = 3.3 k DEVICE UNDER TEST CL CL Includes Jig Capacitance
1.
OUT
Applied to high-speed product, LH28F800SG-L70.
Fig. 12 Transient Equivalent Testing Load Circuit
- 26 -
LH28F800SG-L (FOR SOP) 6.2.3 DC CHARACTERISTICS
SYMBOL ILI ILO PARAMETER Input Load Current Output Leakage Current NOTE 1 1 VCC = 2.7 to 3.6 V TYP. MAX. 0.5 0.5 VCC = 5.00.5 V UNIT TYP. MAX. 1 10 A A TEST CONDITIONS VCC = VCC Max. VIN = VCC or GND VCC = VCC Max. VOUT = VCC or GND CMOS inputs VCC = VCC Max. CE# = RP# = VCC0.2 V TTL inputs VCC = VCC Max. CE# = RP# = VIH RP# = GND0.2 V IOUT (RY/BY#) = 0 mA CMOS inputs VCC = VCC Max. CE# = GND f = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) IOUT = 0 mA TTL inputs VCC = VCC Max. CE# = GND f = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) IOUT = 0 mA VPP = 2.7 to 3.6 V VPP = 5.00.5 V VPP = 12.00.6 V VPP = 2.7 to 3.6 V VPP = 5.00.5 V VPP = 12.00.6 V CE# = VIH VPP VCC VPP > VCC RP# = GND0.2 V VPP VPP VPP VPP VPP VPP = = = = = = 2.7 to 3.6 V 5.00.5 V 12.00.6 V 2.7 to 3.6 V 5.00.5 V 12.00.6 V
100 ICCS VCC Standby Current 1, 3, 6 2 ICCD VCC Deep Power-Down Current
100
A
2
mA
1
12
16
A
25
50
mA
ICCR
VCC Read Current
1, 5, 6
30
65
mA
ICCW
VCC Word Write or Set Lock-Bit Current
1, 7
VCC Block Erase or Clear Block Lock-Bits Current ICCWS VCC Word Write or Block ICCES Erase Suspend Current IPPS VPP Standby or Read Current IPPR VPP Deep Power-Down IPPD Current ICCE IPPW VPP Word Write or Set Lock-Bit Current
1, 7
17 17 12 17 17 12 6 15 200 5 80 80 30 40 40 30 200
--
--
-- 35 30 -- 30 25 10 15 200 5
mA mA mA mA mA mA mA A A A mA mA mA mA mA mA A
1, 2 1 1
--
1, 7
VPP Block Erase or Clear Block Lock-Bits Current IPPWS VPP Word Write or Block IPPES Erase Suspend Current IPPE
--
1, 7 1
-- 80 30 -- 40 30 200
VPP = VPPH1/2/3
- 27 -
LH28F800SG-L (FOR SOP) 6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL VIL VIH PARAMETER Input Low Voltage Input High Voltage NOTE 7 7 VCC = 2.7 to 3.6 V MIN. MAX. -0.5 0.8 VCC 2.0 +0.5 0.4 VCC = 5.00.5 V UNIT MIN. MAX. -0.5 0.8 V VCC 2.0 V +0.5 0.45 V TEST CONDITIONS
VOL
Output Low Voltage
3, 7
VOH1
Output High Voltage (TTL)
3, 7
2.4 0.85 VCC VCC -0.4 1.5
2.4 0.85 VCC VCC -0.4 1.5
V
VOH2
Output High Voltage (CMOS)
V V V
3, 7
VCC = VCC Min. IOL = 5.8 mA (VCC = 5 V), IOL = 2.0 mA (VCC = 3.3 V, 2.7 V) VCC = VCC Min. IOH = -2.5 mA (VCC = 5 V), IOH = -2.0 mA (VCC = 3.3 V, 2.7 V) VCC = VCC Min. IOH = -2.5 A VCC = VCC Min. IOH = -100 A
VPP Lockout Voltage during Normal Operations VPP Voltage during VPPH1 Word Write, Block Erase or Lock-Bit Operations VPP Voltage during VPPH2 Word Write, Block Erase or Lock-Bit Operations VPP Voltage during VPPH3 Word Write, Block Erase or Lock-Bit Operations VLKO VCC Lockout Voltage VPPLK VHH RP# Unlock Voltage
4, 7
2.7
3.6
--
--
V
4.5
5.5
4.5
5.5
V
11.4 2.0 8 11.4
12.6
11.4 2.0
12.6
V V
12.6
11.4
12.6
V
Set permanent lock-bit Override block lock-bit
NOTES :
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25C. These currents are valid for all product versions (packages and speeds). ICCWS and ICCES are specified with the device deselected. If reading or word writing in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. Includes RY/BY#. Block erases, word writes, and lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.) and VPPH3 (min.), and above VPPH3 (max.). 5. Automatic Power Saving (APS) reduces typical ICCR to 1 mA at 5 V VCC and 3 mA at 2.7 to 3.6 V VCC in static operation. CMOS inputs are either VCC0.2 V or GND0.2 V. TTL inputs are either VIL or VIH. Sampled, not 100% tested. Permanent lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the permanent lock-bit is set or RP# = VIH. Block erases and word writes are inhibited when the corresponding block lock-bit is set and RP# = VIH or the permanent lock-bits is set. Block erase, word write, and lock-bit configuration operations are not guaranteed with VIH < RP# < VHH and should not be attempted.
6. 7. 8.
2.
3. 4.
- 28 -
LH28F800SG-L (FOR SOP) 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)
* VCC = 2.7 to 3.0 V, TA = 0 to +70C
VERSIONS SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH PARAMETER Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First 2 2 3 3 3 3 3 NOTE
LH28F800SG-L70 MIN. 100 100 100 600 45 0 45 0 20 0 MAX.
LH28F800SG-L10 MIN. 120 120 120 600 55 0 55 0 25 0 MAX.
UNIT ns ns ns ns ns ns ns ns ns ns
* VCC = 3.30.3 V, TA = 0 to +70C VERSIONS SYMBOL PARAMETER tAVAV Read Cycle Time tAVQV Address to Output Delay tELQV CE# to Output Delay tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First NOTE LH28F800SG-L70 MIN. 85 MAX. 85 85 600 40 0 40 0 15 0 0 0 20 0 45 LH28F800SG-L10 MIN. 100 MAX. 100 100 600 45 UNIT ns ns ns ns ns ns ns ns ns ns
2 2 3 3 3 3 3
NOTES :
1. 2. 3. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested.
- 29 -
LH28F800SG-L (FOR SOP) 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) (NOTE 1)
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C VERSIONS VCC0.25 V LH28F800SG-L70 VCC0.5 V SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH PARAMETER Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First 2 2 3 3 3 3 3 0 10 0 0 NOTE MIN. 70 70 70 400 40 0 55 0 10 0 0 55 0 15 MAX.
(NOTE 5) (NOTE 5) (NOTE 4)
UNIT MAX. 100 100 400 50 ns ns ns ns ns ns ns ns ns ns
LH28F800SG-L70 LH28F800SG-L10 MIN. 80 80 80 400 45 0 55 MAX. MIN. 100
NOTES :
1. 2. 3. 4. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. 5. See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
- 30 -
LH28F800SG-L (FOR SOP)
Standby VIH ADDRESSES (A) VIL
Device Address Selection Address Stable
Data Valid
tAVAV
VIH CE# (E) VIL tEHQZ
OE# (G)
VIH tGHQZ VIL tELQV VIH
WE# (W) VIL tELQX DATA (D/Q) (DQ0 - DQ15) VOH VOL High Z tAVQV
tGLQV tGLQX tOH High Z
Valid Output
VCC tPHQV VIH RP# (P) VIL
Fig. 13 AC Waveform for Read Operations
- 31 -
LH28F800SG-L (FOR SOP) 6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
* VCC = 2.7 to 3.0 V, TA = 0 to +70C
SYMBOL tAVAV tPHWL tELWL tWLWH tPHHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH
VERSIONS PARAMETER NOTE Write Cycle Time RP# High Recovery to WE# Going Low 2 CE# Setup to WE# Going Low WE# Pulse Width RP# VHH Setup to WE# Going High 2 VPP Setup to WE# Going High 2 Address Setup to WE# Going High 3 Data Setup to WE# Going High 3 Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High 2, 4 RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
LH28F800SG-L70 MIN. MAX. 100 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0
LH28F800SG-L10 MIN. MAX. 120 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0
UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* VCC = 3.30.3 V, TA = 0 to +70C SYMBOL tAVAV tPHWL tELWL tWLWH tPHHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH VERSIONS PARAMETER Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width RP# VHH Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High NOTE 2 LH28F800SG-L70 MIN. MAX. 85 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0 LH28F800SG-L10 MIN. MAX. 100 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0 UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2 2 3 3
2, 4 2, 4
3. 4.
NOTES :
1. Read timing characteristics during block erase, word write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, word write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
2.
- 32 -
LH28F800SG-L (FOR SOP) 6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.) (NOTE 1)
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C VCC0.25 V VERSIONS VCC0.5 V SYMBOL tAVAV tPHWL tELWL PARAMETER Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low 2 NOTE MIN. 70 1 10 2 2 3 3 40 100 100 40 40 5 5 10 30 90 0 2, 4 2, 4 0 0 0 0 0 MAX.
(NOTE 5)
LH28F800SG-L70
(NOTE 6) (NOTE 6)
UNIT MAX. ns s ns ns ns ns ns ns ns ns ns 90 ns ns ns ns ns
LH28F800SG-L70 MIN. 80 1 10 40 100 100 40 40 5 5 10 30 90 MAX.
LH28F800SG-L10 MIN. 100 1 10 40 100 100 40 40 5 5 10 30 0 0 0
tWLWH WE# Pulse Width tPHHWH RP# VHH Setup to WE# Going High tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High
NOTES :
1. Read timing characteristics during block erase, word write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, word write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, word write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
2. 3. 4.
6.
- 33 -
LH28F800SG-L (FOR SOP)
(NOTE 1)
(NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH ADDRESSES (A) VIL VIH CE# (E) VIL VIH OE# (G) VIL tWHWL VIH WE# (W) VIL tWLWH tDVWH tWHDX High Z tPHWL tWHRL DIN DIN Valid SRD DIN tWHQV1/2/3/4 tELWL tWHEH tWHGL AIN tAVAV AIN tAVWH tWHAX
VIH DATA (D/Q) VIL VOH RY/BY# (R) VOL
tPHHWH VHH RP# (P) VIH VIL tVPWH VPPH1/2/3 VPP (V) VPPLK VIL
tQVPH
tQVVL
NOTES :
1. 2. 3. 4. 5. 6. VCC power-up and standby. Write block erase or word write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command.
Fig. 14 AC Waveform for WE#-Controlled Write Operations
- 34 -
LH28F800SG-L (FOR SOP) 6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITES OPERATIONS (NOTE 1)
* VCC = 2.7 to 3.0 V, TA = 0 to +70C VERSIONS SYMBOL PARAMETER NOTE tAVAV Write Cycle Time tPHEL RP# High Recovery to CE# Going Low 2 tWLEL WE# Setup to CE# Going Low tELEH CE# Pulse Width tPHHEH RP# VHH Setup to CE# Going High 2 tVPEH VPP Setup to CE# Going High 2 tAVEH Address Setup to CE# Going High 3 tDVEH Data Setup to CE# Going High 3 tEHDX Data Hold from CE# High tEHAX Address Hold from CE# High tEHWH WE# Hold from CE# High tEHEL CE# Pulse Width High tEHRL CE# High to RY/BY# Going Low tEHGL Write Recovery before Read tQVVL VPP Hold from Valid SRD, RY/BY# High 2, 4 RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 tQVPH * VCC = 3.30.3 V, TA = 0 to +70C SYMBOL tAVAV tPHEL tWLEL tELEH tPHHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVPH VERSIONS PARAMETER NOTE Write Cycle Time RP# High Recovery to CE# Going Low 2 WE# Setup to CE# Going Low CE# Pulse Width RP# VHH Setup to CE# Going High 2 VPP Setup to CE# Going High 2 Address Setup to CE# Going High 3 Data Setup to CE# Going High 3 Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High 2, 4 RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
3. 4.
LH28F800SG-L70 MIN. MAX. 100 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0
LH28F800SG-L10 MIN. MAX. 120 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0
UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
LH28F800SG-L70 MIN. MAX. 85 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0
LH28F800SG-L10 MIN. MAX. 100 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0
UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES :
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, word write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
2.
- 35 -
LH28F800SG-L (FOR SOP) 6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITES OPERATIONS (contd.) (NOTE 1)
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C VCC0.25 V VERSIONS VCC0.5 V SYMBOL PARAMETER tAVAV Write Cycle Time tPHEL tWLEL tELEH tPHHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVPH RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width RP# VHH Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to RY/BY# Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 2, 4 2, 4 NOTE MIN. 70 1 0 2 2 3 3 50 100 100 40 40 5 5 0 25 90 0 0 0 0 0 0 MAX.
(NOTE 5)
LH28F800SG-L70
(NOTE 6) (NOTE 6)
UNIT MAX. ns s ns ns ns ns ns ns ns ns ns 90 ns ns ns ns ns
LH28F800SG-L70 LH28F800SG-L10 MIN. 80 1 0 50 100 100 40 40 5 5 0 25 90 0 0 0 MAX. MIN. 100 1 0 50 100 100 40 40 5 5 0 25
2
NOTES :
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, word write, or lock-bit configuration. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, word write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics.
2. 3. 4.
6.
- 36 -
LH28F800SG-L (FOR SOP)
(NOTE 1)
(NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH ADDRESSES (A) VIL VIH WE# (W) VIL VIH OE# (G) VIL tEHEL VIH CE# (E) VIL tELEH tDVEH tEHDX High Z tPHEL tEHRL DIN DIN Valid SRD DIN tEHQV1/2/3/4 tWLEL tEHWH tEHGL AIN tAVAV AIN tAVEH tEHAX
VIH DATA (D/Q) VIL VOH RY/BY# (R) VOL
tPHHEH VHH RP# (P) VIH VIL tVPEH VPPH1/2/3 VPP (V) VPPLK VIL
tQVPH
tQVVL
NOTES :
1. 2. 3. 4. 5. 6. VCC power-up and standby. Write block erase or word write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command.
Fig. 15 AC Waveform for CE#-Controlled Write Operations
- 37 -
LH28F800SG-L (FOR SOP) 6.2.7 RESET OPERATIONS
VOH RY/BY# (R) VOL VIH RP# (P) VIL tPLPH (A) Reset During Read Array Mode VOH RY/BY# (R) VOL VIH RP# (P) VIL tPLPH (B) Reset During Block Erase, Word Write, or Lock-Bit Configuration tPLRH
2.7 V/3.3 V/5 V VCC VIL VIH RP# (P) VIL (C) VCC Rising Timing t235VPH
Fig. 16 AC Waveform for Reset Operation Reset AC Specifications (NOTE 1) SYMBOL tPLPH tPLRH PARAMETER RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during Block Erase, Word Write, or Lock-Bit Configuration 2, 3 NOTE VCC = 2.7 to 3.6 V MIN. MAX. 100 20 28 (2.7 V VCC) 100 100 VCC = 5.00.5 V MIN. MAX. 100 12 UNIT ns s
VCC 2.7 V to RP# High t235VPH VCC 3.0 V to RP# High VCC 4.5 V to RP# High
4
ns
NOTES :
1. 2. These specifications are valid for all product versions (packages and speeds). If RP# is asserted while a block erase, word write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. 4. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. When the device power-up, holding RP#-low minimum 100 ns is required after VCC has been in predefined range and also has been in stable there.
- 38 -
LH28F800SG-L (FOR SOP) 6.2.8 BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4)
* VCC = 2.7 to 3.0 V, TA = 0 to +70C SYMBOL PARAMETER NOTE 2 2 2 2 2 VPP = 2.7 to 3.0 V MIN. 49 1.7 TYP.(NOTE 1) 63 2.1 3.0 44 3.8 12.6 34.1 MAX. VPP = 5.00.5 V MIN. 20 0.7 TYP.(NOTE 1) 28 1.0 2.0 28 2.6 10.5 20.2 MAX. VPP = 12.00.6 V MIN. TYP.(NOTE 1) MAX. 15.4 0.56 1.9 24.4 2.3 10.5 20.2 UNIT s s s s s s s
tWHQV1 Word Write Time tEHQV1 Block Write Time tWHQV2 tEHQV2 Block Erase Time
tWHQV3 Set Lock-Bit Time tEHQV3 tWHQV4 Clear Block Lock-Bits tEHQV4 Time tWHRH1 Word Write Suspend tEHRH1 Latency Time to Read tWHRH2 Erase Suspend Latency tEHRH2 Time to Read
* VCC = 3.30.3 V, TA = 0 to +70C SYMBOL tWHQV1 tEHQV1 tWHQV2 tEHQV2 tWHQV3 PARAMETER Word Write Time Block Write Time Block Erase Time NOTE 2 2 2 2 2 VPP = 3.30.3 V MIN. TYP.(NOTE 1) MAX. 35 1.2 45 1.5 2.1 31 2.7 9 24.3 VPP = 5.00.5 V MIN. TYP.(NOTE 1) MAX. 14 0.5 20 0.7 1.4 20 1.8 7.5 14.4 VPP = 12.00.6 V MIN. TYP.(NOTE 1) MAX. 11 0.4 1.3 17.4 1.6 7.5 14.4 UNIT s s s s s s s
Set Lock-Bit Time tEHQV3 tWHQV4 Clear Block Lock-Bits tEHQV4 Time tWHRH1 Word Write Suspend tEHRH1 Latency Time to Read tWHRH2 Erase Suspend Latency tEHRH2 Time to Read
NOTES :
1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. Excludes system-level overhead. 3. 4. These performance numbers are valid for all speed versions. Sampled, not 100% tested.
2.
- 39 -
LH28F800SG-L (FOR SOP) 6.2.8 BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.) (NOTE 3, 4)
* VCC = 5.00.25 V, 5.00.5 V, TA = 0 to +70C SYMBOL PARAMETER NOTE 2 2 2 2 2 VPP = 5.00.5 V MIN. 10 0.4 TYP.(NOTE 1) 14 0.5 1.3 18 1.6 7.5 14.4 MAX. VPP = 12.00.6 V MIN. TYP.(NOTE 1) MAX. 7.5 0.25 1.2 15 1.5 6 14.4 UNIT s s s s s s s
tWHQV1 Word Write Time tEHQV1 Block Write Time tWHQV2 tEHQV2 Block Erase Time
tWHQV3 Set Lock-Bit Time tEHQV3 tWHQV4 Clear Block Lock-Bits Time tEHQV4 tWHRH1 Word Write Suspend Latency Time to Read tEHRH1 tWHRH2 tEHRH2 Erase Suspend Latency Time to Read
NOTES :
1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. Excludes system-level overhead. 3. 4. These performance numbers are valid for all speed versions. Sampled, not 100% tested.
2.
- 40 -
LH28F800SG-L (FOR SOP)
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products LH28F800SGN - L70 Device Density 800 = 8 M-bit Architecture S = Symmetrical Block Power Supply Type G = SmartVoltage Technology Operating Temperature = 0 to 70C Access Speed (ns) 70 : 70 ns (5.00.25 V), 80 ns (5.00.5 V), 85 ns (3.30.3 V), 100 ns (2.7 to 3.0 V) 10 : 100 ns (5.00.5 V), 100 ns (3.30.3 V), 120 ns (2.7 to 3.0 V) Package N = 44-pin SOP (SOP044-P-0600)
OPTION
ORDER CODE
VALID OPERATIONAL COMBINATIONS VCC = 2.7 to 3.0 V VCC = 3.30.3 V VCC = 5.00.5 V 50 pF load, 1.35 V I/O Levels 100 ns 120 ns 50 pF load, 1.5 V I/O Levels 85 ns 100 ns 100 pF load, TTL I/O Levels 80 ns 100 ns
VCC = 5.00.25 V 30 pF load, 1.5 V I/O Levels 70 ns
1 2
LH28F800SGN-L70 LH28F800SGN-L10
- 41 -
PACKAGING
44 SOP (SOP044-P-0600)
44_ 0.40.1
1.27TYP.
0.15
M
44
23
16.0 0.4
13.2 0.2
2.7 0.2
1
1.275
28.2 0.2
22 0.15
0.15 0.05
Package base plane 0.1 0.150.1
(14.4)

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